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etrontech em639165 etron technology, inc. no. 6, technology rd. v, science-based industrial park, hsinchu, taiwan 30077, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc., reserves the right to make changes to its products and specifications without notice. 8mega x 16bits sdram preliminary (rev 1.0, 2/2001) features single 3.3 0.3v power supply fast clock rate - pc133: 133 mhz (cl3) - pc100: 100 mhz (cl2) fully synchronous operation referenced to clock rising edge 4-bank operation controlled by ba0, ba1 (bank address) programmable mode registers - /cas latency: 2 or 3 - burst length: 1, 2, 4, 8 or full page - burst type: interleaved or linear burst byte control ? dqml and dqmu random column access auto precharge / all banks precharge controlled by a10 auto and self-refresh self-refresh mode: standard and low power 4096 refresh cycles/64ms interface: lvttl 54-pin 400 mil plastic tsop ii package key specifications em639165 - 75/8 t ck2 clock cycle time (min., cl=2) 10/10 ns t ck3 clock cycle time (min., cl=3) 7.5/8 ns t ac2 access time (max., cl=2) 6/6 ns t ac3 access time (max., cl=3) 5.4/6 ns t ras row active time (max.) 45/48 ns t rc row cycle time(min.) 67.5/70 ns overview em639165 is a high-speed synchronous dynamic random access memory (sdram), organized as 4 banks x 2,097,152 words x 16 bits. all inputs and outputs are referenced to the rising edge of clk. it achieves very high-speed data rates up to 133mhz, and is suitable for main memories or graphic memories in computer systems. for handheld device application, we also provide a low power option, with self-refresh current under 800 m a. pin assignment (top view) ordering information part number speed grade self refresh current (max.) em639165ts-75 pc133/cl3 2 ma em639165ts-75l pc133/cl3 800 m a EM639165TS-8 pc100/cl2 2 ma EM639165TS-8l pc100/cl2 800 m a vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd dqml /we /cas /ras /cs ba0 ba1 a10(ap) a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc dqmu clk cke nc a11 a9 a8 a7 a6 a5 a4 vss
em639165 preliminary rev 1.0 feb. 2001 2 block diagram address buffer a0-11 ba0,1 control signal buffer /cs /ras /cas /we clk cke clock buffer control circuitry i/o buffer dq0-15 mode register dqm memory array bank #0 4096 x512x16 cell array memory array bank #1 cell array memory array bank #2 cell array memory array bank #3 cell array 4096 x512x16 4096 x512x16 4096 x512x16
preliminary rev 1.0 feb. 2001 em639165 3 pin function clk input master clock: all other inputs are referenced to the rising edge of clk cke input clock enable: cke controls internal clock.when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self-refresh. after self-refresh mode is started, cke becomes asynchronous input. self-refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-11 input a0-11 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-11. the column address is specified bya0-8. a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre , read , write commands. input / output input din mask / output disable: when dqm(u/l) is high in burst write, din for the current cycle is masked. when dqm(u/l) is high in burst read, dout is disabled at the next but one cycle. vdd,vss power supply power supply for the memory array and peripheral circuitry. vddq,vssq power supply vddq and vssq are supplied to the output buffers only. data in and data out are referenced to the rising edge of clk. dq0-15 dqmu/l
em639165 preliminary rev 1.0 feb. 2001 4 activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deac- tivated after the burst read (auto-precharge, reada ). write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read / write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. basic functions the em639165 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh opt ion, and precharge option, respectively . to know the detailed definition of commands, please see the command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @ refresh command a10 precharge option @ precharge or read/write command clk define basic command
preliminary rev 1.0 feb. 2001 em639165 5 h=high level, l=low level, v=valid, x=don't care, n=clk cycle number note: 1. a7-a9 =0, a0-a6 =mode address command truth table command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a11 a10 a0-9 desel hxhxxxxxxx no operation nop hxlhhhxxxx act hxllhhvvvv pre hxllhlvxlx prea hxllhl xhx write hxlhllvvlv write a hxlhll vvhv read hxlhlhvvlv reada hxlhlhvvhv auto-refresh refa hhll lhxxxx self-refresh entry refs hl ll lhxxxx self-refresh exit refsx l hhxxxxxxx l hlhhhxxxx mode register set mr s h x l l l l l l l v*1 x burst terminate tbst hx l hhl xx xx deselect row address entry & bank active single bank precharge precharge all banks column address entry &write column address entry & write with auto-precharge column address entry & read column address entry & read with auto-precharge
em639165 preliminary rev 1.0 feb. 2001 6 function truth table hxxxx desel nop l h h h x nop nop l h h l tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refa auto-refresh*5 llll op-code, mode-add mrs mode register set*5 hxxxx desel nop l h h h x nop nop l h h l tbst nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal llll op-code, mode-add mrs illegal current state /cs /ras /cas /we address command action idle row active ba ba
preliminary rev 1.0 feb. 2001 em639165 7 function truth table (continued) current state /cs /ras /cas /we address command action read write l h h l tbst l h l h ba, ca, a10 read /reada l h l l ba, ca, a10 write / writea l l h l ba, a10 pre / prea l l l h x refa illegal llll op-code, mode-add mrs illegal h x x x x desel lhhhx nop l l h h ba, ra act h x x x x desel l h h h x nop nop (continue burst to end) l h h l tbst l h l h ba, ca, a10 read / reada l h l l ba, ca, a10 write / writea terminate burst, latch ca,begin write, determine auto-precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l mrs illegal op-code, mode-add read, determine auto-precharge*3 terminate burst, latch ca,begin terminate burst, latch ca,begin nop (continue burst to end) terminate burst, precharge bank active / illegal*2 terminate burst, latch ca,begin write, determine auto-precharge*3 read, determine auto-precharge*3 terminate burst, latch ca,begin terminate burst nop (continue burst to end) nop (continue burst to end) ba ba
em639165 preliminary rev 1.0 feb. 2001 8 function truth table (continued) current state /cs /ras /cas /we address command action read with auto precharge h x x x x desel lhhhx nop l h h l tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / write a illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal write with auto precharge h x x x x desel l h h h x nop nop (continue burst to end) l h h l tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add illegal mrs nop (continue burst to end) nop (continue burst to end) nop (continue burst to end) bank active / illegal*2 ba ba
preliminary rev 1.0 feb. 2001 em639165 9 function truth table (continued) current state /cs /ras /cas /we address command action pre - charging row activating h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea nop*4 (idle after trp) l l l h x refa illegal llll op-code, mode-add mrs illegal h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal ba ba
em639165 preliminary rev 1.0 feb. 2001 10 function truth table (continued) current state /cs /ras /cas /we address command action hxxx x desel nop write recovering lhhh x nop nop lhhl tbst illegal*2 lhlx ba, ca, a10 read / write illegal*2 llhh ba, ra act illegal*2 llhl ba, a10 pre / prea illegal*2 l l l h x refa illegal llll op-code, mode-add mrs illegal refreshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal llll op-code, mode-add mrs illegal ba ba
preliminary rev 1.0 feb. 2001 em639165 11 function truth table (continued) mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal llll op-code, mode-add mrs illegal current state /cs /ras /cas /we address command action ba
em639165 preliminary rev 1.0 feb. 2001 12 function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) lhlhhhx l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down hxxxxxx l h x x x x x exit power down to idle l l x x x x x nop (maintain power down) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk susspend at next cycle*3 l hxxxxx l l x x x x x maintain clk suspend exit self-refresh (idle after trc) invalid exit clk susspend at next cycle*3
preliminary rev 1.0 feb. 2001 em639165 13 mode register burst length, burst type and /cas latency can be pro- grammed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when all banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. r: reserved for future use bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 1 2 4 8 r r r fp 1 2 4 8 r r r r 0 1 burst type sequential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 0 0 0 ltmode bt bl 0 0 cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 latency mode /cas latency 2 3 r r r r r r /cs /ras /cas /we ba0,1 a11-a0 clk v fp: full page power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm high and nop condition at the inputs. 2. maintain stable power, stable clock, and nop input con- ditions for a minimum of 200s. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation.
em639165 preliminary rev 1.0 feb. 2001 14 initial address bl a2 a1 a0 sequential interleaved column addressing 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 -00 -01 -10 -11 --0 0123456701234567 1234567010325476 2345670123016745 3456701232107654 4567012345670123 5670123454761032 6701234567452301 7012 0123 1230 2301 30 01 7654 0123 1032 2301 32 01 --1 12 10 3456 3210 10 10 8 4 2 command address clk read y q0 q1 q2 q3 write y d0 d1 d2 d3 /cas latency burst length burst length dq burst type cl= 3 bl= 4
preliminary rev 1.0 feb. 2001 em639165 15 operational description bank activate the sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indi- cated by the row addresses a0-11. the minimum activation interval between one bank and the other bank is trrd. maximum 2 act commands are allowed within trc , although the number of banks which are active concurrently is not limited. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea, pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a0-a9,a11(x4), a0-9(x8), a0-8(x16) , and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl after reada. (need to keep tras min.) the next act command can be issued after (bl + trp) from the previous reada. bank activation and precharge all (bl=4, cl=3) command clk a0-9 a10 ba0,1 dq act xa xa 00 read y 0 00 qa0 qa1 qa2 qa3 act xb xb 01 pre trrd trcd 1 act xb xb 01 precharge all tras trp trcmin 2 act command / trcmin a11 xa xb xb
em639165 preliminary rev 1.0 feb. 2001 16 clk command a0-9 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 qa0 qa1 qa2 qa3 qb0 qb1 qb2 act xb xb 10 pre 0 00 trcd /cas latency burst length a11 xa xb clk command a0-9 a10 ba0,1 dq act xa xa 00 read y 1 00 qa0 qa1 qa2 qa3 act xa xa 00 internal precharge start trcd trp a11 xa xa bl bl + trp clk command act read dq dq cl=3 cl=2 internal precharge start timing qa1 qa2 qa3 qa0 bl qa1 qa2 qa3 qa0 multi bank interleaving read (bl=4, cl=3) read with auto-precharge (bl=4, cl=3) read auto-precharge timing (bl=4)
preliminary rev 1.0 feb. 2001 em639165 17 write after trcd from the bank activation, a write command can be issued. 1st input data is set at the same cycle as the write. following (bl -1) data are written into the ram, when the burst length is bl. the start address is specified by a0-a9,a11(x4), a0-9(x8), a0-8(x16) and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind con- tinuous input data by interleaving the multiple banks. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, the autoprecharge (writea) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge begins at twr after the last input data cycle. (need to keep tras min.) the next act command can be issued after trp from the internal precharge timing. clk command a0-9 a10 ba0,1 dq act xa xa 00 write y 1 00 da0 da1 da2 da3 trcd act xa xa 00 internal precharge starts a11 xa xa xa xa clk command a0-9 a10 ba0,1 dq act xa 00 write y 00 write y 00 10 da0 act xb xb 10 0 10 trcd trcd pre xa a11 xb 0 xa 0 00 pre 0 da1 da2 da3 db0 db1 db2 db3 twr trp write with auto-precharge (bl=4) multi bank interleaving write (bl=4)
em639165 preliminary rev 1.0 feb. 2001 18 burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any bank. random column access is allowed read to read interval is minimum 1 clk.. clk command a0-9 a10 ba0,1 dq yi qai0 qaj1 qbk0 qbk1 qaj0 qbk2 qal0 qal1 qal2 qal3 read read read read yj yk yl 00 00 00 10 00 01 a11 dqm control write control clk command a0-9 a10 ba0,1 q read yi 0 00 qai0 write yj 0 00 d daj0 daj1 daj2 daj3 dqm a11 [ read interrupted by write ] burst read operation can be interrupted by write of any bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 1 cycle after write assertion. read interrupted by read (bl=4, cl=3) read interrupted by write (bl=4, cl=3)
preliminary rev 1.0 feb. 2001 em639165 19 [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same bank . read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas read interrupted by precharge (bl=4) latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=4. clk cl=3 command dq read pre q0 q1 q2 command dq read pre q0 cl=2 command dq read pre q0 q1 q2 command dq read pre q0 command dq read pre q0 q1 command dq read pre q0 q1
em639165 preliminary rev 1.0 feb. 2001 20 [read interrupted by burst terminate] similarly to the precharge, a burst terminate command can inter- rupt the burst read operation and disable the data output. the terminated bank remains active. read interrupted by terminate (bl=4) read to tbst interval is minimum 1 clk. a tbst command to output disable latency is equivalent to the /cas latency. clk cl=3 command dq read tbst q0 q1 q2 command dq read q0 cl=2 command dq read q0 q1 q2 command dq read q0 command dq read q0 q1 command dq read q0 q1 tbst tbst tbst tbst tbst
preliminary rev 1.0 feb. 2001 em639165 21 [ write interrupted by write ] burst write operation can be interrupted by new write of any bank. random column access is allowed. write to write interval is minimum 1 clk. clk command a0-9 a10 ba0,1 dq write yi 0 00 write yk 0 10 dai0 daj0 daj1 dbk0 write yj 0 00 dbk1 dbk2 write yl 0 00 dal0 dal1 dal2 dal3 a11 clk command a0-9 a10 ba0,1 dq write yi 0 00 qaj0 read yj 0 00 qaj1 dai0 dbk0 dbk1 dqm write yk 0 10 read yl 0 00 qal0 a11 write interrupted by write (cl=3,bl=4) [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". write interrupted by read (cl=3,bl=4)
em639165 preliminary rev 1.0 feb. 2001 22 [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank.write recovery time(twr) is required from the last data to pre command. during write recovery, data inputs must be masked by dqm. write interrupted by precharge (bl=4) clk command a0-9,11 a10 ba0-1 dq write ya 0 00 act xa 0 00 da 0 da 1 pre 0 00 act xa 0 00 twr trp dqm clk command a0-9,11 a10 ba0-1 dq write ya 0 00 act xa 0 00 da 0 da 1 tbst write yb 0 00 db 0 db 1 db 2 db 3 [write interrupted by burst terminate] burst terminate command can terminate burst write operation.in this case, the write recovery time is not required and the bank remains active. write to tbst interval is minimum 1 clk. write interrupted by terminate (bl=4)
preliminary rev 1.0 feb. 2001 em639165 23 [write with auto-precharge interrupted by write or read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after trp. auto-precharge interruption by a command to the same bank is inhibited. write interrupted by write to another bank (bl=4) clk command a0-9,11 a10 ba0-1 dq db 0 db 1 db 2 db 3 write ya 1 00 da 0 da 1 write yb 0 10 bl twr trp act xa xa 00 interrupted auto-precharge activate clk command a0-9,11 a10 ba0-1 dq write ya 1 00 da 0 da 1 read yb 0 10 bl twr trp act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 write interrupted by read to another bank (cl=2,bl=4)
em639165 preliminary rev 1.0 feb. 2001 24 clk command a0-9,11 a10 ba0-1 dq read ya 1 00 qa0 qa1 read yb 0 10 bl trp act xa xa 00 interrupted auto-precharge activate qb0 qb1 qb2 qb3 [read with auto-precharge interrupted by read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after trp. auto-precharge interruption by a command to the same bank is inhibited. read interrupted by read to another bank (cl=2,bl=4) [full page burst] full page burst length is available for only the sequential burst type. full page burst read or write is repeated untill a prec harge or a burst terminate command is issued. in case of the full page burst, a read or write with auto-precharge command is illegal. [single write] when single write mode is set, burst length for write is always one, independently of burst length defined by (a2-0).
preliminary rev 1.0 feb. 2001 em639165 25 auto-refresh auto refresh single cycle of auto-refresh is initiated with a refa (/cs= /ras= / cas= l, /we= /cke= h) command. the refresh address is gen- erated internally. 4096 refa cycles within 64ms refresh 128m bit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trc. any command must not be sup- plied to the device before trc from the refa command. clk /cs /ras /cas /we cke a0-11 ba0,1 auto refresh on all banks minimum trfc nop or deselect auto refresh on all banks
em639165 preliminary rev 1.0 feb. 2001 26 self-refresh self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self- refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input ,all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke=h. after trc from the 1st clk egde following cke=h, all banks are in the idle state and a new command can be issued, but desel or nop commands must be asserted till then. clk /cs /ras /cas /we cke a0-11 ba0,1 self refresh entry self refresh exit x 00 stable clk nop new command minimum trfc for recovery
preliminary rev 1.0 feb. 2001 em639165 27 clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. clk command cke command cke standby power down active power down pre nop nop nop nop nop nop act clk command dq cke write read d0 d1 d2 d3 q0 q1 q2 q3 ext.clk cke int.clk tih tis tih tis power down by cke dq suspend by cke (cl=2)
em639165 preliminary rev 1.0 feb. 2001 28 dqm function(cl=3) dqm control dqm is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqm(u,l) masks input data word by word. dqm(u,l) to write mask latency is 0. during reads, dqm(u,l) forces output to hi-z word by word. dqm(u,l) to output hi-z latency is 2. clk command dq write d0 d2 d3 dqm read q0 q1 q3 masked by dqm(u,l)=h disabled by dqm(u,l)=h
preliminary rev 1.0 feb. 2001 em639165 notes: 1. vih(max)=5.5v for pulse width less than 10ns. 2. vil(min)=-1.0v for pulse width less than 10ns. symbol parameter unit min. typ. max. vdd supply voltage 3.0 3.3 3.6 v vss 0 0 vddq supply voltage for output 3.0 3.3 3.6 v vssq 0 0 vih*1 high-level input voltage all inputs 2.0 vddq +0.3 v vil*2 low-level input voltage all inputs -0.3 0.8 v symbol parameter condition rating unit vdd supply voltage with respect to vss -0.5 - 4.6 v vddq supply voltage for output -0.5 - 4.6 v vi input voltage -0.5 - 4.6 v vo output voltage -0.5 - 4.6 v io output current 50 ma pd power dissipation ta = 25 ?c 1000 topr operating temperature 0 - 70 tstg storage temperature -65 - 150 with respect to vssq with respect to vss with respect to vssq symbol parameter test condition ci(a) input capacitance, address pin ci(c) input capacitance, contorl pin @ 1mhz 1.4v bias 200mv swing vcc=3.3v ci(k) input capacitance, clk pin ci/o input capacitance, i/o pin unit pf pf pf pf (ta=0 - 70 ?c ,unless otherwise noted) (ta=0 -7 0 ?c,vdd=vddq=3.3 ?.3v,vss=vssq=0v,unless otherwise noted) 2.5 2.5 2.5 4.0 5.0 5.0 4.0 6.5 supply voltage supply voltage for output ?c ?c 0 v v mw min. max. 29 absolute maximum ratings capacitance recommended operating conditions
em639165 preliminary rev 1.0 feb. 2001 note: 1. icc(max) is specified at the output open condition. 2. input signals are changed one time during 30ns. symbol parameter test conditions unit min. max. voh (dc) high-level output voltage (dc) ioh=-2ma 2.4 v vol (dc) low-level output voltage (dc) iol= 2ma 0.4 v ioz off-state output current q floating vo= 0 -- vddq -10 10 a input current vih = 0 -- vddq +0.3v -10 10 a i i (ta=0 - 70 ? c, vdd=vddq=3.3 0.3v,vss=vssq=0v, unless otherwise noted) symbol item all bank active tclk = min bl=4, cl=3, iol=0ma icc4 burst current icc1 operating current trc=min, tclk=min bl=1,iol=0ma (ta=0 - 70 ? c, vdd=vssq=3.3 0.3v,vss=vssq=0v, unless otherwise noted) precharge standby current in non-power down mode icc2n cke=vilmax tclk=15ns icc2ns cke=vihmin clk=vilmax(fixed) precharge standby current in power down mode icc2p cke=vihmin tclk=15ns(note) icc2ps cke=vihmin tclk=vilmax(fixed) icc3ns cke=vihmin tclk=vilmax(fixed) icc3n cke=/cs=vihmin tclk=15ns(note) -75 20 15 2 1 20 30 100 110 130 -8 20 15 2 1 20 30 95 100 120 active standby current unit icc6 self-refresh current cke < 0.2v 22 ma icc5 trc=min, tclk=min auto-refresh current 160 160 ma ma ma ma ma ma ma ma 160 130 ma ma standard low-power 800 800 a test condition max. 30 average supply current from vdd ac operating conditions and characteristics
preliminary rev 1.0 feb. 2001 em639165 31 ac timing requirements any ac timing is referenced to the input signal passing through 1.4v. input pulse levels:0.8v-2.0v input timing measurement level:1.4v clk dq 1.4v 1.4v symbol parameter unit -75 tclk clk cycle time cl=2 cl=3 tch clk high pulse width n tcl clk low pulse width n tt transition time of clk tis input setup time (all inputs) tih input hold time (all inputs) n trc row cycle time trcd row to column delay tras row active time trp row precharge time twr write recovery time trrd act to act delay time trsc mode register set cycle time tref refresh interval time -8 (ta=0 - 70 ? c, vdd=vddq=3.3 0.3v,vss=vssq=0v, unless otherwise noted) max. 10 64 100k max. 10 64 100k trfc refresh cycle time min. 10 7.5 2.5 1.8 1 2.5 1 67.5 45 20 15 15 15 20 75 2 1 min. 10 8 3 3 1 70 48 20 20 20 20 20 80 ns ns s s ns s ms ns ns ns ns ns ns ns ns ns
em639165 preliminary rev 1.0 feb. 2001 note: 1. if clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter. v out 50pf output timing measurement reference point clk 1.4v 1.4v dq s ymbol parameter -75 -8 tac access time from clk cl=2 cl=3 toh output hold time from clk max. 6 5.4 5.4 tolz delay time , output low- impedance from clk tohz note *1 tohz tac clk dq 1.4v 1.4v toh tolz cl=2 cl=3 min. 3 3 3 0 (ta=0 - 70 ? c, vdd=vddq=3.3 0.3v,vss=vssq=0v, unless otherwise noted) delay time , output high- impedance from clk max. 6 6 6 3 0 3 min. 3 unit ns ns ns ns ns ns 32 switching characteristics output load condition
preliminary rev 1.0 feb. 2001 em639165 33 burst write (single bank) @bl=4 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc t rcd tras twr trp trcd twr act#0 pre#0 act # 0 write#0 pre#0 write#0
em639165 preliminary rev 1.0 feb. 2001 34 burst write (multi bank) @bl=4 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 0 x y x x 0 0 d0 d0 d0 d0 0 trc t rcd tras twr trp trcd twr act#0 writ e # 0 pre#0 act# 0 write#0 pre#0 x x x 1 act#1 trrd trcd y 1 d1 d1 d1 d1 writea#1 (auto-precharge) act#1 x x x 1 trc
preliminary rev 1.0 feb. 2001 em639165 35 burst read (single bank) @bl=4 cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 q0 q0 q0 q0 0 x y x x 0 0 q0 q0 q0 q0 0 trc t rcd tras trp trcd act#0 read#0 pre#0 act# 0 read#0 pre#0 tras
em639165 preliminary rev 1.0 feb. 2001 36 burst read (multiple bank) @bl=4 cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 q0 q0 q0 q0 1 x y x x 0 0 q0 q0 q0 q0 0 trc t rcd trcd act#0 reada# 0 reada# 1 act# 0 read#0 pre#0 x x x 1 trrd act#1 y q1 q1 q1 q1 trcd x x x 1 act# 1 trc tras
preliminary rev 1.0 feb. 2001 em639165 37 write interrupted by write @bl=4 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 d0 d0 1 y 0 d0 d0 d0 d0 0 t rcd act#0 write# 0 write# 0 pre#0 x x x 1 trrd act#1 y d0 d1 d1 d1 x x x 1 act# 1 y 0 write# 0 writea# 1 interrupt same bank interrupt other bank interrupt other bank twr
em639165 preliminary rev 1.0 feb. 2001 38 read interrupted by read @bl=4,cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 q0 q0 1 y 0 q1 q1 q0 q0 t rcd act#0 read#0 read#0 x x x 1 trrd act#1 y q0 q1 q1 q1 x x x 1 act# 1 y 1 read#1 reada# 1 interrupt other bank trcd interrupt same bank interrupt other bank q0 q0
preliminary rev 1.0 feb. 2001 em639165 39 write interrupted by read, read interrupted by write @bl=4,cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 y 1 d1 d1 d1 d1 1 trcd act#0 write# 0 write# 1 pre#1 x x x 1 trrd act#1 q1 q1 y 1 twr read#1 trcd
em639165 preliminary rev 1.0 feb. 2001 40 write/read terminated by precharge @bl=4,cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 y 0 q0 q0 0 trcd act#0 write# 0 read#0 pre#0 0 pre#0 twr x x x 0 act#0 trp 0 tras trcd trp x x x act#0 trc te rminate te rminate
preliminary rev 1.0 feb. 2001 em639165 41 write/read terminated by burst terminate @bl=4,cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 d0 y 0 q0 q0 0 trcd act#0 write# 0 read#0 term pre#0 y 0 term d0 d0 d0 d0 write#0 twr
em639165 preliminary rev 1.0 feb. 2001 42 single write burst read @bl=4,cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 q0 q0 t rcd act#0 write# 0 read#0 q0 q0 y 0
preliminary rev 1.0 feb. 2001 em639165 43 power-up sequesce and intialize clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 pre all refa act# 0 mrs refa 0 0 0 ma x x x 200s refa trp trfc minimum 8 refa cycles nop trfc trsc power on
em639165 preliminary rev 1.0 feb. 2001 44 auto refresh clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pre all refa y 0 d0 d0 d0 d0 write#0 x x x 0 act#0 trp trfc trcd all banks must be idle before refa is iss ued.
preliminary rev 1.0 feb. 2001 em639165 45 self refresh clk / cs / ras / cas / we cke dqm a0-8, a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pre all self refres h e ntry self refres h exit x x x 0 act#0 trp all banks must be idle before refs is iss ued. trfc
em639165 preliminary rev 1.0 feb. 2001 46 clk suspension @bl=4,cl=2 clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x 0 y 0 d0 q0 q0 t rcd act#0 write# 0 read#0 q0 y 0 d0 d0 d0 internal clk suspended q0 internal clk suspended
preliminary rev 1.0 feb. 2001 em639165 47 power down clk / cs / ras / cas / we cke dqm a0-8 a10 a9,11 ba0,1 dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pre all act# 0 x 0 x x standby power down active power down
em639165 preliminary rev 1.0 feb. 2001 48 54 pin tsop ii package outline drawing information y s b e a a 1 a 2 l l 1 c 54 1 d e h e 0.254 ? l l 1 27 28 symbol dimension in inch dimension in mm min normal max min normal max a-- 0.047 -- 1.194 a1 0.002 0.00395 0.0059 0.05 0.1 0.150 a2-- 0.0411 -- 1.044 b 0.012 0.015 0.016 0.3 0.35 0.40 c 0.0047 0.0065 0.0083 0.120 1.165 0.210 d 0.872 0.8755 0.879 22.149 22.238 22.327 e 0.3960 0.400 0.4040 10.058 10.16 10.262 e - 0.0315 - - 0.80 - he 0.462 0.466 0.470 11.735 11.8365 11.938 l 0.016 0.020 0.0235 0.406 0.50 0.597 l1 - 0.033 - - 0.84 - s - 0.035 - - 0.88 - y - - 0.004 - - 0.10 q 0 - 5 0 - 5 notes: 1. dimension d & e do not include interiead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension s includes end flash. 4. controlling dimension: mm

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